1. Field of the Invention
The present invention relates to a configuration of an internal voltage generation circuit for internally generating an internal voltage used in a semiconductor device such as a semiconductor integrated circuit device. More particularly, the present invention relates to a semiconductor device including a reference voltage generation circuit for generating a reference voltage independent of an external power supply voltage and an internal voltage generation circuit for generating an internal voltage at a necessary level in accordance with the reference voltage.
2. Description of the Background Art
In semiconductor integrated circuit devices, a reference voltage generation circuit generating a reference voltage for setting a level of an internal voltage has been employed in many cases, in order to convert a level of an externally applied voltage to generate the internal voltage of a desired level. The reference voltage generation circuit can maintain a level of a reference voltage at a constant level without being affected by variation in an external power supply voltage and therefore, a level of an internal voltage set in accordance with the reference voltage can be kept constant to operate internal circuitry in a stable manner.
FIG. 16 is a block diagram schematically showing a configuration of a reference voltage generation section in a conventional semiconductor integrated circuit device. In FIG. 16, DRAM (dynamic random access memory) is shown as a typical semiconductor integrated circuit device. As shown in FIG. 16, a reference voltage generating circuitry includes: a constant current generation circuit 900 generating a constant current Icst; and reference voltage generation circuits 902, 904, 906 and 908, connected to the constant current generation circuit 900, performing current/voltage conversion on the constant current Icst to generate reference voltages Vrefs, Vrefi, Vrefd and Vrefb, respectively. Internal voltages used in the DRAM are generated in accordance with the reference voltages Vrefs, Vrefi, Vrefd and Vrefb.
An internal voltage generation circuitry further includes: a voltage down converter 910 generating an array power supply voltage Vdds supplied to an array circuit 920 in accordance with the reference voltage Vrefs; a voltage down converter 912 generating a periphery power supply voltage Vddi supplied to a peripheral circuit 922 in accordance with the reference voltage Vrefi; a boosted voltage generation circuit 914 generating a boosted voltage Vpp in accordance with the reference voltage Vrefd; and a boosted voltage generation circuit 916 generating a boosted voltage Vddb in accordance with the reference voltage Vrefb.
The boosted voltage generation circuit 914 is provided with: a voltage divider circuit 911 dividing the boosted voltage Vpp generated by the boosted voltage generation circuit 914; and a detection circuit 913 comparing an output voltage of the voltage divider circuit 911 with the reference voltage Vrefb to control a voltage boosting operation of the boosted voltage generation circuit 914 in accordance with the comparison result. The boosted voltage Vpp from the boosted voltage generation circuit 914 is supplied to, for example, a boosted voltage utilizing circuit 924 such as a word line drive circuit.
The boosted voltage generation circuit 916 is provided with: a voltage divider circuit 915 voltage-dividing the boosted voltage Vddb; and a detection circuit 917 comparing an output voltage of the voltage divider circuit 915 with the reference voltage Vrefb to activate/deactivate a voltage boosting operation of the boosted voltage generation circuit 916 in accordance with the comparison result. The boosted voltage Vddb is supplied to a boosted voltage utilizing circuit 926 including, for example, a bit line isolation instructing signal generation circuit, a bit line equalize signal generation circuit and others.
The array circuit 920 includes, for example, a memory cell array; a sense amplifier circuit performing sensing and amplification of data of memory cells. The peripheral circuit 922 includes a control circuit generating an internal operation control signal and others.
Levels of the power supply voltages Vdds and Vddi generated by voltage down converters 910 and 912 are determined in accordance with the reference voltages Vrefs and Vrefi, respectively. Likewise, levels of boosted voltages Vpp and Vddb are determined by voltage-division ratios of the voltage divider circuits 911 and 915 and levels of the reference voltages Vrefd and Vrefb. Therefore, the voltage down converters 910 and 912 and the boosted voltage generation circuits 914 and 916 are required to generate the voltages Vdds, Vddi, Vpp and Vddb in a stable manner in order to operate the circuits 920, 922, 924 and 926 in a stable manner. That is, since levels of these voltages are determined by the reference voltages, the reference voltage generation circuits 902, 904, 906 and 908 have to generate the reference voltages Vrefs, Vrefi, Vrefd and Vrefb in a stable manner. Especially, it is very important to generate the reference voltages Vrefs, Vrefi, Vrefd and Vrefb with high precision since operating characteristics of internal circuits such as the array circuit 920 are determined by levels of the voltages Vdds, Vddi, Vpp and Vddb.
FIG. 17 is a graph showing a characteristic of a reference voltage. In FIG. 17, one of the reference voltages Vrefs, Vrefi, Vrefd and Vrefb shown in FIG. 16 is represented as a reference voltage Vref. As an externally applied voltage (external power supply voltage) rises, a constant current Icst from the constant current generation circuit 900 increases, and the reference voltage Vref rises with rise in the externally applied voltage (external power supply voltage). The region in which a voltage level of the reference voltage Vref rises is called a linear region.
When the externally applied voltage (external power supply voltage) reaches a certain voltage level, the constant current Icst from the constant current generation circuit 900 shown in FIG. 16 becomes constant and in response, the reference voltage Vref is made constant as well. Accordingly, when the externally applied voltage increases beyond the certain voltage value, a level of the reference voltage Vref is kept at a constant value independent of a level of the externally applied voltage (external power supply voltage). The region in which the reference voltage Vref is at a constant level is called a flat region.
Internal circuitry such as the array circuit is operated in the flat region in which the reference voltage Vref is constant. Thus, a reference voltage is generated stably independently of variations in the externally applied voltage (external power source voltage), thereby enabling generation of a stable internal voltage.
FIG. 18 is a block diagram schematically showing a configuration of a reference voltage generating circuit shown in FIG. 16. The reference voltage generation circuits 902, 904, 906 and 908 have substantially the same configurations as one another, except for that levels of the reference voltages generated by these circuits are different from one another. In FIG. 18, the reference voltage generation circuit 930 is shown representably.
As shown in FIG. 18, the reference voltage generation circuit 930 includes: a current source 930a for generating a constant current corresponding to the constant current Icst from the constant current generating circuit 900; a trimmable impedance element 930b for converting the constant current Icst from the current source 930a to a voltage level; and a tuning mechanism 930c for adjusting an impedance value of the trimmable impedance element 930b. A stabilization capacitance 930d for stabilizing the reference voltage Vref is provided at an output node 930f of the reference voltage generation circuit 930.
In the reference voltage generation circuit 930, a current flows through the trimmable impedance element 930b from the current source 930a normally. Hence, in order to reduce a current in a standby state, an impedance value of the trimmable impedance element 930b is set so sufficiently large as to sufficiently reduce an amount of the current Icst supplied by the current source 930a. For the constant current of a minute current amount, the stabilization capacitance 930d is provided for holding the reference voltage Vref in a stable manner without an influence of noise. The reference voltage Vref rises according to an externally applied voltage after power is switched on as shown in FIG. 17. Since an internal voltage (Vdds or the like) is generated in accordance with a reference voltage Vref, a rise time (a time required for a voltage to reach a definite state) of the internal voltage (Vdds or the like) conforms to a rise time of the reference voltage.
While the reference voltage Vref has to be set to a value as designed, variations in the reference voltage occur in level in actual semiconductor devices because of fluctuations in a fabrication process parameter or the like. Causes for the variations are, for example, variations in threshold voltage and operating current of transistors in the constant current generation circuit and the reference voltage generation circuit 930. The level of the reference voltage Vref is checked for each semiconductor chip fabricated actually. The tuning mechanism 930c is incorporated in the reference voltage generation circuit 930 in order to adjust the reference voltage level to an intended voltage level in accordance with the checking result. In a case where the trimmable impedance element 930b is constituted, for example, utilizing a channel resistance of a MOS transistor (an insulated gate field effect transistor), the channel resistance is required to be sufficiently large in order to supply a minute current (for example, an MOS transistor with a total channel length L of hundreds of xcexcm for a channel width of 4 xcexcm has to be equivalently used), which causes a problem that a layout area of the trimmable impedance element 930b becomes large.
Further, the tuning mechanism 930c is required to be provided for adjusting an impedance value of the trimmable impedance element 930b, which causes another problem of additionally increasing a layout area of the reference voltage generation circuit. The tuning mechanisms 930c are included in the respective reference voltage generation circuits 902, 904, 906 and 908 shown in FIG. 16. Hence, the reference voltages Vref (Vrefs, Vrefi, Vrefd and Vrefb) require individual voltage level adjustment operations for each device in the final step of a device fabrication process. The trimming step of adjusting a reference voltage level is performed in a test step after completion of device fabrication at a wafer level, thus resulting in increase in length of a test time.
For example, Japanese Patent Laid-Open No. 5-47184 discloses a configuration in which a reference voltage generation circuit is provided commonly to a plurality of internal voltage circuits. In this prior art, however, adjustment of an internal voltage level is performed for each internal voltage generation circuit to individually generate an internal voltage at an intended level. Therefore, characteristics of each internal voltage generation circuit have to be adjusted at a design stage, thereby causing a problem of deteriorating design efficiency.
Further, an internal voltage is level-converted for comparison with a reference voltage, in order to generate the internal voltages at different levels from the same reference voltage, and a through current is required to conduct for the level conversion normally. The internal voltage generation circuit is to supply a voltage direct to an internal circuit, and is set to consume a large current, thereby causing a problem that a through current is large corresponding to a large consumed current.
It is an object of the present invention to provide a semiconductor device capable of generating a necessary reference voltage in a stable manner with a reduced occupancy area.
It is another object of the present invention to provide a semiconductor device capable of shortening a test time for adjusting a level of a reference voltage.
A semiconductor device according to the present invention includes: a constant current generation circuit for generating a constant current; a current/voltage conversion circuit according to the constant current from the constant current generation circuit for generating a constant voltage; a voltage distribution circuit for receiving the constant voltage to generate at least one reference voltage; and an internal voltage generation circuit for generating a plurality of internal voltages in accordance with the reference voltage received from the voltage distribution circuit.
The current/voltage conversion circuit generating a constant voltage is provided to the voltage distribution circuit and one or more reference voltages are generated using the constant voltage to further generate an internal voltage or internal voltages from the one or more reference voltages. Hence, there is no necessity to provide a current/voltage conversion circuit to each reference voltage, thereby decreasing a layout area. Furthermore, the current/voltage conversion circuit is provided commonly to one or more reference voltages and a level(s) of the reference voltage(s) can be adjusted only by level tuning of one constant voltage, thereby enabling reduction of time in tuning of a voltage level.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.